Recent advances in miniaturization technologies for semiconductor circuits has led to an increase in the circuit sizes of field-programmable gate arrays (FPGAs), which has in turn led to an increase in the size of FPGA configuration data (hereinafter simply referred to as config data). Additionally, partial configuration technology is being adopted, in which a single set of config data for an FPGA is partitioned into a plurality of partition data in order to modify the functions of a portion of a running FPGA, without stopping the other functions within the FPGA.
FIG. 12 illustrates an exemplary transmission system. The transmission system 100 illustrated in FIG. 12 includes a plurality of nodes 101 such as transmission apparatus, and a central management apparatus 102. The nodes 101 and the central management apparatus 102 are communicably connected via a network 103.
Each node 101 includes a plurality of FPGAs 111 and memory units 112. Config data for an FPGA 111 is stored in each memory unit 112. Each FPGA 111 executes a configuration process on the basis of config data stored in its memory unit 112. The central management apparatus 102 provides unified management of the config data for all FPGAs 111 in all nodes 101 on the network 103. Additionally, the central management apparatus 102 includes memory 121 and a management controller 122. The memory 121 may be realized by a hard disk drive (HDD) or semiconductor memory, for example, and config data for each type of FPGA 111 is stored in the memory 121. The management controller 122 provides overall control of the central management apparatus 102. The management controller 122 retrieves config data corresponding to the types of FPGAs 111 in a particular node 101 from the memory 121, and transmits the retrieved config data to the node 101 containing those FPGAs 111.
When a node 101 receives config data from the central management apparatus 102, the received config data is stored in the memory units 112 of the corresponding FPGAs 111. Additionally, the node 101 causes its FPGAs 111 to execute respective configuration processes on the basis of the config data stored in their memory units 112.
For more information, see Japanese Laid-open Patent Publication No. 2001-306343 and Japanese Laid-open Patent Publication No. 2005-190305.